In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down the device dimensions on semiconductor wafers (e.g., at submicron levels). In order to accomplish such high device packing density, smaller and smaller features sizes are required. This may include the width and spacing of interconnecting lines, spacing and diameter of contact holes and the surface geometry such as corners and edges of various features.
The requirement of small features with close spacing between adjacent features requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist and an exposing source (such as optical light, x-rays, etc.) illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The lithographic coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive image of the subject pattern. Exposure of the coating through a photomask causes the image area to become either more or less soluble (depending on the coating) in a particular solvent developer. The more soluble areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
The ability to reduce the size of computer chips while increasing packing densities and performance is driven by lithography technology and metallization processes and is especially critical to ultra large scale integration (ULSI) circuits. ULSI circuits require responsive changes in interconnection technology which is considered a very demanding aspect of ULSI technology. High density demands for ULSI integration require planarizing layers with minimal spacing between conductive lines.
Single damascene is a technique developed to address disadvantages (e.g., poor metal step coverage, residual metal shorts, low yields, uncertain reliability, and poor ULSI integration extendability) associated with traditional etch back methods. Damascene, an art which has been employed for centuries in the fabrication of jewelry, has been adapted for application in the semiconductor industry. Damascene basically involves the formation of a trench which is filled with a metal. Thus, damascene differs from traditional etch back methods which involve building up a metal wiring layer and filling the interwiring spaces with a dielectric material.
Single damascene techniques offer the advantage of improved planarization as compared to etch back methods; however, single damascene is time consuming in that numerous process steps are required. Undesirably, an interface exists between the conductive via and conductive wiring. Moreover, adequate planarization layers containing an interwiring spacing less than 0.35 μm are difficult to achieve.
An improvement to single damascene is dual damascene which involves substantially simultaneous formation of a conductive via and conductive wiring. The dual damascene technique requires less manipulative steps than the single damascene technique and eliminates the interface between the conductive via and conductive wiring which is typically formed by the single damascene technique. In very and ultra large scale integration (VLSI and ULSI) circuits, an insulating or dielectric material, such as silicon oxide, of the semiconductor device in the dual damascene process is patterned with several thousand openings for the conductive lines and vias which are filled with metal, such as aluminum, and serve to interconnect active and/or passive elements of the integrated circuit. The dual damascene process also is used for forming multilevel signal lines of metal, such as copper, in the insulating layers, such as polyimide, of a multilayer substrate on which semiconductor devices are mounted.
As previously mentioned, dual damascene is a multi-level interconnection process in which, in addition to forming the grooves of single damascene, conductive via openings also are formed. In a standard dual damascene process, the insulating layer is coated with a first photoresist which is exposed through a first mask with an image pattern of the via openings and the pattern is anisotropically etched in the upper half region of the insulating layer. The photoresist is now exposed through a second mask with an image pattern of the conductive line openings, after being aligned with the first mask pattern to encompass the via openings. In anisotropically etching the openings for the conductive lines in the upper half of the insulating material, the via openings already present in the upper half are simultaneously etched and replicated in the lower half of the insulating material. After the etching is complete, both the vias and line openings are filled with metal. Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating process steps.
A conventional dual damascene process is illustrated in FIGS. 1–3 in connection with a semiconductor structure 10. FIG. 1 illustrates a perspective view of an insulative oxide layer 14 formed on a semiconductor substrate 12. A photoresist layer 16 is formed on the insulative oxide layer 14. The photoresist layer 16 is patterned using conventional techniques to form first openings 18. Anisotropic reactive ion etching (RIE) is performed to form vias 20 (FIG. 2) in the insulative oxide layer 14. Subsequently, the photoresist 16 is exposed to a second mask with an image pattern of conductive lines and is transformed into photoresist 22 (FIG. 2).
Following exposure to the second mask, the photoresist layer 22 has second openings 24 (FIG. 2) about the size of the ultimate trench therein. Anisotropic RIE is again performed to form a trench 26 (FIG. 3) in the insulative oxide layer 14.
Other conventional dual damascene processes employ a multi-layer dielectric/insulative layer including an etch stop layer formed in between a top and a bottom oxide layer. This type of semiconductor structure must be subjected to multiple etch processes in order to fully transfer the via and conductive line patterns from upper photoresist layers to the underlying dielectric multi-layer structure.
Although these known dual damascene techniques offers advantages over other processes for forming interconnections, the repetitive sequence of patterning and etching can be cumbersome and the likelihood of damage to a partially fabricated semiconductor structure increases with each sequence of patterning and etching.
In view of the above, there is an unsatisfied need for a modified dual damascene process involving fewer processing steps. More specifically, there is an unsatisfied need for a dual damascene process having a single etch step.